IEEE International Symposium on VLSI Design and Test

IEEE International Symposium on VLSI Design and Test

Join Marvell at the 28th IEEE International Symposium on VLSI Design and Test (VDAT) 2024


The IEEE International Symposium provides opportunities for academia, researchers, startups, and industrial practitioners to share new ideas, experiences, and knowledge in various fields of VLSI Design and Testing.

Presentation

Tutorial Track: Standard cell characterization
Topic: Life cycle and development of custom Standard cells
Date: Sunday, September 1, 2024
Time: 9:30 a.m.
Marvell Presenter: Aquib Quraishi, Staff Engineer

Tutorial Track
Topic: Impact of Design for Test on the Production of a Chip
Date: September 1, 2024
Time: 11.30 a.m.
Marvell Presenters: Aanand Venkatachalam, Director and Suraj Chathoth, Principle Engineer

Keynote: Transforming Cloud Infrastructure for the AI era
Date: Monday, September 2, 2024
Time: 11:30 a.m.
Marvell Keynote: Navin Bishnoi, Country Head

Where to Find Us

IEEE International Symposium on VLSI Design and Test
Vellore Institute of Technology, Vellore, INDIA
September 1-3, 2024

Contact Us

We believe better partnerships help to build better technologies. Let’s connect and see what we can design together!

Thank You for Your Interest

We will be in touch with you soon!